module CodeRecog(sig, clk, rst, out);
	parameter		T0 = 3'b000;
	parameter		T1 = 3'b001;
	parameter		T2 = 3'b010;
	parameter		T3 = 3'b011;
	parameter		T4 = 3'b100;
	
	input			clk;
	input			sig;
	input			rst;
	output	reg		out;
	reg		[2:0]	current_state;
	reg		[2:0]	next_state;
	reg		[2:0]	cnt;
	reg				cnt_up;
	wire			in;
	
	assign in = sig & (!cnt_up);
	
	//状态机
	always @(posedge clk or negedge rst) begin
		if(!rst)
			current_state <= T0;
		else
			current_state <= next_state;
	end
	always @(in, current_state) begin
		case(current_state)
			T0: begin
				out = 0;
				if(in) next_state = T1; else next_state <= T0;
			end
			T1: begin
				out = 0;
				if(in) next_state = T2; else next_state <= T0;
			end
			T2: begin
				out = 0;
				if(in) next_state = T3; else next_state <= T0;
			end
			T3: begin
				out = 0;
				if(in) next_state = T0; else next_state <= T4;
			end
			T4: begin
				out = 1;
				if(in) next_state = T1; else next_state <= T0;
			end
			default: begin
				out = 0;
				next_state <= T0;
			end
		endcase
	end
	
	//计数器
	always @(posedge clk or negedge rst) begin
		if(!rst) begin
			cnt <= 0;
			cnt_up <= 0;
		end
		else if(cnt == 6)
			cnt_up <= 1;
		else if(out)
			cnt <= cnt + 1;
		else
			cnt <= cnt;
	end
	

endmodule